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为解决数字逻辑实验课程案例缺少人工智能与硬件结合新兴技术、实验内容缺乏前瞻性与综合性问题，该文设计实现了基于FPGA脉动阵列的YOLO神经网络推理平台，基于该平台软硬件实现过程，构建了一系列实验案例，并通过测试验证了平台的实用性。该平台可以覆盖计算机类本科生多门硬件课程专题实验、开放创新实验以及毕业设计，有助于培养学生将人工智能与硬件设计相结合的创新思想，以及灵活运用课程知识动手解决实际工程问题的能力。
Abstract：[Objective] The digital logic experiment course, essential for computer and electrical engineering undergraduates, has long emphasized foundational hardware concepts like logic gates, combinational circuits, and sequential circuits. However, the omission of emerging technologies integrating artificial intelligence(AI) and hardware from course materials has resulted in experimental content that lacks foresight, innovation, and interdisciplinary depth. This gap limits students' ability to connect theoretical knowledge with cutting-edge industry practices, particularly in AI-driven hardware acceleration. To address this, we propose a systolic array platform using FPGAs to accelerate YOLO neural network inference. The platform modernizes the curriculum by embedding AI-hardware co-design principles, enhancing students' ability to tackle real-world engineering problems through hands-on experimentation. [Methods] The platform employs a co-design approach integrating hardware and software components. Hardware utilizes an FPGA-based systolic array to accelerate inference for the YOLO neural network(widely adopted for real-time object detection). The systolic array architecture is selected for its inherent parallelism and efficiency in matrix multiplication/addition operations fundamental to neural networks. Software implements control and data transmission interfaces using Verilog HDL, enabling communication between the host system and FPGA accelerator. The platform supports structured experimental cases covering serial communication, state machine design, and Verilog-based circuit implementation. These guide students through designing, synthesizing, and debugging hardware circuits while introducing model quantization, pruning, and distillation for hardware-aware neural network optimization. [Results] The platform was successfully implemented and tested, demonstrating practicality and effectiveness for enhancing the digital logic course. Students gain hands-on experience in hardware circuit design/optimization for AI applications, specifically enabling them to: 1) Deepen understanding of hardware concepts(e.g., adders, multipliers, systolic arrays) by implementing them in neural network acceleration contexts; 2) Engage with mainstream AI technologies(e.g., YOLO) and learn hardware-oriented model optimization; 3) Develop proficiency in Verilog HDL and EDA tools(circuit design, synthesis, place-and-route, timing analysis, on-board debugging). The platform's "one platform, multiple objectives" model supports diverse topic exploration within a unified framework. [Conclusions] This study bridges traditional digital logic education with modern AI-hardware integration. Embedding YOLO acceleration into FPGA experiments enriches the curriculum and cultivates students' interdisciplinary problem-solving skills. Key innovations include the systolic array's adaptive data reshaping mechanism and integrating industry-standard AXI protocols into pedagogical tools. Future work will extend the platform to distributed FPGA clusters for large-scale model training and develop modules for emerging technologies like neuromorphic computing. These efforts position the digital logic course as a cornerstone of AI-driven hardware education, equipping students with skills critical for evolving technological landscapes.
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Basic Information:
DOI：10.16791/j.cnki.sjg.2025.07.030
China Classification Code:TN79-4;TP18
Citation Information:
[1]王今雨,高海峰,安健等.人工智能赋能的数字逻辑实验平台构建与实现[J].实验技术与管理,2025,42(07):232-239.DOI:10.16791/j.cnki.sjg.2025.07.030.
Fund Information:
2024年西安交通大学本科教学改革研究项目(2413Z); 2024年度教育部-华为“智能基座”2.0课程建设项目(24ZNJZ014); 全国高等院校计算机基础教育研究会课题(QG/2024/CBZZ1101-03197)